module top_module (
    input clk,
    input areset,
    input x,
    output z
); 

    reg [1:0]   state;
    reg [1:0]   nxt_state;

    localparam A = 0;
    localparam B = 1;

    // State transition logic (combinational)
    always @(*) begin
        case (state)
            A:begin
                if(x)
                    nxt_state = B;
                else
                    nxt_state = A;
            end
            B:begin
                nxt_state = B;
            end
          default: begin
            nxt_state = A;
          end
        endcase
    end

    // State flip-flops (sequential)
    always @(posedge clk or posedge areset) begin
        if(areset)
            state   <=  A;
        else begin
            state   <=  nxt_state;
        end  
    end
	
    //output logic
    assign  z    =   state == A ? x:~x ;

endmodule
